Mark Fuselier is senior vice president of Technology and Product Engineering at AMD. He is responsible for silicon and packaging technology development and new product introduction engineering. Fuselier has more than 25 years of semiconductor industry experience and has been involved in the development and production of process technology generations spanning from 0.35um through 7nm across multiple fabs and product families. He has played a central role in the development and productization of computing solutions such as multi-core CPU and GPU SoC integration, heterogenous APUs, 2.5D chip-packaging, and chiplet System in Package (SiP) integration. Fuselier holds a Master of Science degree in Electrical Engineering and Master of Business Administration from the University of Texas at Austin. He is a member of IEEE and the Electron Devices Society.
Mark Fuselier is senior vice president of Technology and Product Engineering at AMD. He is responsible for silicon and packaging technology development and new product introduction engineering. Fuselier has more than 25 years of semiconductor industry experience and has been involved in the development and production of process technology generations spanning from 0.35um through 7nm across multiple fabs and product families. He has played a central role in the development and productization of computing solutions such as multi-core CPU and GPU SoC integration, heterogenous APUs, 2.5D chip-packaging, and chiplet System in Package (SiP) integration. Fuselier holds a Master of Science degree in Electrical Engineering and Master of Business Administration from the University of Texas at Austin. He is a member of IEEE and the Electron Devices Society.
Many of the world's biggest challenges - medical research, climate change, electrical grid efficiency - are relying on continued scaling of High-Performance Compute Capability. This comes at a time when our industry faces many challenges in driving this much needed scaling as classic Moore's scaling slow to a crawl. To meet this challenge, the industry will need to drive all innovation across all elements of the ecosystem - from foundry to packaging, and thermal solutions to Design. This keynote will highlight the key innovation required over the next 10 years to continue to drive performance scaling required to enable the compute bandwidth required to solve our toughest problems.