ISES USA 2023
HomeWhy AttendAdvisory BoardWhy SponsorSpeakersVenueAgendaContactSponsorsAbout ISESCovid-19Register Now
Website Design by Cibus
Babak
Sabi Ph.D.
Intel Corporation
SVP & GM of Assembly and Test Technology Development
Dr. Babak Sabi is a Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development. Babak joined Intel in 1984. Prior to leading ATTD, he oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices. Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.
Dr. Babak Sabi is a Senior Vice President and the General Manager of Assembly & Test Technology Development (ATTD) at Intel Corporation. Since 2009, he has been responsible for the company’s packaging, assembly, and test process technology development. Babak joined Intel in 1984. Prior to leading ATTD, he oversaw Intel’s Corporate Quality Network from 2002 to 2009 where he led product reliability, customer satisfaction and quality business practices. Babak received his Ph.D. in solid state electronics from Ohio State University in 1984. He has authored ten papers on reliability physics and has received five Intel Achievement Awards. He currently holds two patents.
Upcoming Events
May 9th
|
9:15 – 9:45
Heading
Advanced Packaging Ecosystem: Challenges and Solutions
Advanced packaging architectures are today widely acknowledged as being increasingly important to drive performance and cost improvements of microelectronics systems. This trend is set to continue as on-package heterogeneous integration of diverse IP from multiple process nodes and multiple foundries will enable new product concepts, decrease time to market and deliver cost/yield benefits. Additionally, novel 3D architectures and continued die-to-die interconnect scaling are opening previously un-achievable concepts for die partitioning. These advanced packaging architectures provide a means to offer improved functional integration, but also present technical challenges across the supply chain [DieàPackageà BoardàSystem]. This presentation will highlight key challenges the industry will have to jointly address to enable the 3D heterogeneous integration future. Key areas of focus will be: (1) Drivers and directions in interconnect scaling, (2) Standardization of die-to-die connections, (3) Package-level integration of optical interconnects, and (4) Advanced substrate developments. The talk will conclude with a call for broad collaboration across industry and academia in multiple areas including technology R&D, design, standardization, and supply chain development.
Full Agenda
Intel Corporation
Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better. To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.
Register Now
